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| Category: |
Engineering |
| Ad Number: |
21446 |
| Date Posted: |
03/12/2012 |
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| Name: |
Bull Groupe |
| Company: |
Bull Groupe - Amesys |
| Address: |
# 09-01, Suntec tower 2 |
| Postal Code: |
038989 |
| Region: |
Southern and Central Singapore |
| Country: |
Singapore |
| Email: |
Reply to Ad |
| Website: |
http://www.bull.com |
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JOB REQUIREMENTS AND RESPONSIBILITIES:
•Functional Verification Engineers, realize pattern Generation for functional, isolation, memory and timing Characterization patterns and basic understanding of the ATE setup. •Understanding of the functional simulation environment, Questasim, Incisive simulator Usage and debugging process. •Proficient in C, C++, Perl and VHDL - Good understanding of MCU and ASIC. Well versed in IC development process and Unix environment, SOC , VHDL , system C , Verilog , modelsim. •Minimum 3 – 5 years of experience and is open for all nationalities.
ADDRESS : 9 Temasek Blvd #09-01 Suntec Tower 2 Singapore 038989
www.bull.com/ |
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