| Profile of Bull_groupe |
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| Name: Bull Groupe |
| Male |
Southern and Central Singapore
Singapore |
| Member since: Mar 12, 2012 |
| Number of Contacts: (0,0) |
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| Bull Groupe is a world leader in the development of hardware and software solutions for strategic markets, including the fields of Defence & Aeronautics, Telecommunications, Transportation, Energy & Industry, Network & Security and Microelectronics.
Our group, so called, BULL which operates in 50 countries
with 8900 employees, 1,600 M$ revenue and several
development centres (France, USA, China, Poland) and
subsidiaries worldwide. |
|
Business Products & Services
Number of ads: 8
| # | Details |
Category |
Price $ |
Advertiser |
|---|
| 1 |
 | Engineering | — | — |
| WANTED: Physical Design Engineers - PHYSICAL DESIGN ENGINEER
Responsibilities:
•Bachelor/Masters Degree in Electrical/Computer
Engineering
•Min 2 years of physical design experience
•Block experience with Synopsys ICC (preferred) or
Cadence/Magma tools.
•Floor-planning, placement, Clock tree synthesis, routing,
RC extraction, timing and power optimization.
•Physical Design experience in ARM based blocks
implementation (ARM7, ARM9, ARM11) is a plus.
Requirements:
•Required skill(s): Backend, Physical, ASIC, timing, STA,
timing analysis.
•At least 2 year(s) of working experience in the related
field is required for this position.
Position Available: Immediately
Salary Range: $ 2500 - $ 6000 (Singapore Dollars)/ Month
(Depending on experience)
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| 2 |
 | Engineering | — | — |
| OFFERED: SASS developer - •We are looking the candidates for Migration project
under a permanent role. The existing application has been
written in SAS6, SAS/AF and SCL has to be migrated to
SAS8.2, SAS/WebAF using Java technology.
•Must be familiar for concept of load balancing will be use
for front-end application. The ETL process is launched by
Unicenter. The ETL code has concept of error handling,
sending mails on error.
•Language / Packages Used SAS 8.2, SAS6.0, JSP,
Servlet, SAS/WebAF, TOMCAT4.1 as servlet container.
Apache as http server.
•Minimum 3 Years of experience is necessary and is
opened for all nationalities.
ADDRESS : 9 Temasek Blvd #09-01 Suntec Tower 2
Singapore
038989
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| 3 |
 | Engineering | — | — |
| OFFERED: DFT Engineer - Job Responsibilities and requirements:
•DFT architecture comprising test mode selection, analog
DFT specification
•Must familiar with IEEE1149.1 Boundary Scan design
•RTL coding for DFT including test muxing logic - Scan
Insertion - ATPG
•Functional Pattern generation
•Pattern debug on ATE - Design Verification for DFT
experience with Boundary scan design using Synopsys BSD
Compiler experience with scan insertion using Synopsys DFT
Compiler and TetraMAX experience with functional pattern
generation and functional pattern debug on ATE.
•Minimum 3 – 5 years of experience and is open for all
nationalities.
ADDRESS : 9 Temasek Blvd #09-01 Suntec Tower 2
Singapore
038989
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| 4 |
 | Engineering | — | — |
| OFFERED: Verification Engineer - JOB REQUIREMENTS AND RESPONSIBILITIES:
•Functional Verification Engineers, realize pattern
Generation for functional, isolation, memory and timing
Characterization patterns and basic understanding of the ATE
setup.
•Understanding of the functional simulation environment,
Questasim, Incisive simulator Usage and debugging process.
•Proficient in C, C++, Perl and VHDL - Good
understanding of MCU and ASIC. Well versed in IC
development process and Unix environment, SOC , VHDL ,
system C , Verilog , modelsim.
•Minimum 3 – 5 years of experience and is open for all
nationalities.
ADDRESS : 9 Temasek Blvd #09-01 Suntec Tower 2
Singapore
038989
|
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| 5 |
 | Engineering | — | — |
| OFFERED: Validation Engineer - •Experience in Silicon validation using functional and
requirement based validation methodologies
•Good experience in programming languages such as
C/C++, Assembly, Perl / Shell scripting, etc.
•Familiarity with coverage concepts, test plans, post-Si
validation environment, automation, and test writing/debug.
•Experience in using lab equipments such as
Oscilloscopes, Protocol Analyzers/Exercisers, Mid-bus
Probes, Logic Analyzers, JTAG based Debuggers etc.
Exposure to test development on system simulators and
emulators is an advantage
•Writing validation test plans, and then writing tests to
execute those plans
•Development of validation collateral, such as self
checking tests and stressing the peripheral interfaces is often
required to enable test plan execution
•Candidates will need to debug failing tests, then work
with verification engineers, designers and architects to resolve
bugs
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| 6 |
 | Engineering | — | — |
| OFFERED: analog Layout Designer - Key areas of expertise for this position include extensive
knowledge of tool-aided assembly-routing and floor planning,
schematic-to-layout conversion, chip and block-level
verification and chip power-distribution.
Full-custom IC layout (Standard Cell, flash memory, memory
compilers, RF IC, Analog and Digital circuits, and Mixed
signals projects)
REQUIREMENTS:
- Well-versed in Flash Memory/Compiler Architecture at 130,
90, 65,45, 40, 28 nanometer process technology with
minimum 3 years of experience.
- Need Extensive knowledge on EDA tools like Cadence
Virtuoso/Virtuoso-XL,Synopsys CDesigner, Silicon Canvass
Laker.
- Vast experience in verification flows like DRC, LVS, Antenna
- Advance knowledge in assembly-routing - Chip floor planning
using Calypso
ADDRESS : 9 Temasek Blvd #09-01 Suntec Tower 2
Singapore
038989
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| 7 |
 | Engineering | — | — |
| OFFERED: Firmware Engineer - The project requires the following expertise:
•Embedded software development, including optimization
Development is done normally with the IAR Embedded
Workbench.
•6502 micro controller or any 8 bit microcontroller on a
ST25P64 development board Design of audio signal
processing system (encoding and decoding data transmitted
via audio channels) experience in working for mobile device
OS like iOS or Android.
•We are looking for a candidate with minimum 3 years of
experience in the relevant experience.
•We are open for all nationalities.
ADDRESS : 9 Temasek Blvd #09-01 Suntec Tower 2
Singapore
038989
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| 8 |
 | Engineering | — | Owner |
| OFFERED: Physical Design Engineer - •Engineer with a strong profile background in Digital
Physical /BackEnd Design, with strong skills in Logical
Synthesis and STA (Static Timing Analysis), floor planning,
Place and Route (P&R), timing closure, physical verification
(LVS and DRC). Experience of low power design is highly
desirable.
•Candidate must possess at least a Bachelor's Degree,
Post Graduate Diploma, Professional Degree, Engineering
(Electrical/Electronic) or equivalent.
•Required language(s): English
•At least 3 year(s) of working experience in the related
field is required for this position.
•Preferably Junior Executives specializing in Engineering
- Electronics/Communication or equivalent.
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